RVC-based time-predictable faulty caches for safety-critical systems

  • Authors:

  • J. Abella;E. Quinones;F. J. Cazorla;M. Valero;Y. Sazeides

  • Affiliations:

  • Barcelona Supercomput. Center, Barcelona, Spain;Barcelona Supercomput. Center, Barcelona, Spain;Barcelona Supercomput. Center, Barcelona, Spain;Barcelona Supercomput. Center, Barcelona, Spain;Univ. of Cyprus, Nicosia, Cyprus

  • Venue:
  • IOLTS '11 Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium
  • Year:
  • 2011

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Abstract

Technology and Vcc scaling lead to significant faulty bit rates in caches. Mechanisms based on disabling faulty parts show to be effective for average performance but are unacceptable in safety critical systems where worst-case execution time (WCET) estimations must be safe and tight. The Reliable Victim Cache (RVC) deals with this issue for a large fraction of the cache bits. However, replacement bits are not protected, thus keeping the probability of failure still high. This paper proposes two mechanisms to tolerate faulty bits in replacement bits and keep time-predictability by extending the RVC. Our solutions offer different tradeoffs between cost and complexity. In particular, the Extended RVC (ERVC) has low energy and area overheads while keeping complexity at a minimum. The Reliable Replacement Bits (RRB) solution has even lower overheads at the expense of some more wiring complexity.