Journal of Electronic Testing: Theory and Applications
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Electronic design of high-performance digital systems in nano-scale CMOS technologies under Process, power supply Voltage, Temperature and Aging (PVTA) variations is a challenging process. Such variations induce abnormal timing delays leading to systems errors, harmful in safety-critical applications. Performance Failure Prediction (PFP), instead of error detection, becomes necessary, particularly in the presence of aging effects. In this paper, an on-line BIST methodology for PFP in a standard cell design flow is proposed. The methodology is based on abnormal delay detection associated with critical signal paths. PVTA-aware aging sensors are designed. Multilevel simulation is used. Functional and structural test pattern generation is performed, targeting the detection of critical path delay faults. A sensor insertion technique is proposed, together with an up-graded version of a proprietary software tool, DyDA. Finally, a novel strategy for gate-level Aging fault injection is proposed, using the concept of an Aging de-rating factor. Results are presented for a Serial Parallel Interface (SPI) controller, designed with commercial UMC 130nm CMOS technology and Faraday cell library. Only seven sensors are required to monitor unsafe performance operation, due to Negative Bias Thermal Instability (NBTI)-induced aging.