Formal Verification of Galois Field Multipliers Using Computer Algebra Techniques

  • Authors:
  • Jinpeng Lv;Priyank Kalla

  • Affiliations:
  • -;-

  • Venue:
  • VLSID '12 Proceedings of the 2012 25th International Conference on VLSI Design
  • Year:
  • 2012

Quantified Score

Hi-index 0.00

Visualization

Abstract

Finite (Galois) field arithmetic finds applications in cryptography, error correction codes, signal processing, etc. Multiplication usually lies at the core of all Galois field computations and is a high-complexity operation. This paper addresses the problem of formal verification of hardware implementations of modulo-multipliers over Galois fields of the type ${\mathbb{F}}_{2^k}$, using a computer-algebra/algebraic-geometry based approach. The multiplier circuit is modeled as a polynomial system in ${\mathbb{F}}_{2^k}[x_1, x_2, \cdots, x_d]$ and the verification test is formulated as a Nullstellensatz proof over the finite field. A Gr\"obner basis engine is used as the underlying computational framework. The efficiency of Gr\"obner basis computations depends heavily upon the variable (and term) ordering used to represent and manipulate the polynomials. We present a variable (and term) ordering heuristic that significantly improves the efficiency of Gr\"obner basis engines. Using our approach, we can verify the correctness of up to $96$-bit multipliers, whereas contemporary BDDs/SAT/SMT-solver based methods are infeasible.