FPGA Implementation of Cross Virtual Concatenation Transmitter/ Receiver for Data Transmission over Next Generation SDH Systems

  • Authors:

  • Sunanda Manke;Kavita Khare;S. D. Sapre

  • Affiliations:

  • Department of Electronic and Communication Engineering, University Institute of Technology, Barkatullah University, Bhopal, India 462026;Department of Electronics and Communication Engineering, Maulana Azad National Institute of Technology, Bhopal, India 462051;Department of Electronics and Communication Engineering, Maulana Azad National Institute of Technology, Bhopal, India 462051

  • Venue:
  • Journal of Signal Processing Systems
  • Year:
  • 2012

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Abstract

Cross Virtual Concatenation is the new technique proposed for bandwidth efficient transmission of data over SDH networks. SDH networks came into existence for reliable voice transmission. As the demand of data traffic grew in wide area networks, new technologies were developed and standardized for data transmission over SDH networks. The technologies used namely, GFP (generic framing procedure), VCAT (virtual concatenation) and LCAS (link capacity adjustment scheme) enable network operator to provide integrated voice and data services over their legacy SDH infrastructure. Data packets are encapsulated using framing protocols GFP. VCAT is a process of distributing the GFP framed data payload in number of virtual channels of same capacity forming a Virtually Concatenated Group (VCG). LCAS is used for dynamic bandwidth allocation. LCAS enhances the VCAT scheme with hitless in service addition and removal of VC's to/from the VCG.VCAT combines homogeneous virtual channels together which in some cases limits the performance of VCAT. This paper describes the implementation of new concatenation technology named cross virtual concatenation (CVC), which combines heterogeneous VC's together to utilize the SDH bandwidth more efficiently. CVC implementation requires only end node equipments to be upgraded as VCG members travel through the link similar to the conventional VCAT. This paper proposes FPGA implementation of transmitter and receiver circuits for 100 Mbps Ethernet data transmission over next Generation SDH systems using CVC, where two types of VC's namely VC-3 and VC-12 are used for data transmission. Total Transmission delay is calculated as 125 μs. There is no complexity added at the receiver side due to this delay. The receiver is designed for 32 ms differential delay compensation which can be increased up to maximum 256 ms by increasing the buffer size at the receiver.