High sample rate array architectures for median filters

Authors:
C. Chakrabarti
Affiliations:
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ
Venue:
IEEE Transactions on Signal Processing
Year:
1994

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Abstract

Presents high sample rate semi-systolic array architectures for computing 1D and 2D nonrecursive and recursive median filters. A high sample rate is obtained by pipelining the computations in each processor. Although the nonrecursive filters are pipelined by placing latches in the feedforward paths, the recursive filters are restructured to create additional delays in the feedback paths, and then pipelined using the delays as latches