Proceedings of the Fourth Annual Symposium on Logic in computer science
CCS expressions finite state processes, and three problems of equivalence
Information and Computation
Transputers and routers: components for concurrent machines
OUG-13 Proceedings of the 13th Occam user group technical meeting on Real-time systems with transputers
Compositional reachability analysis using process algebra
TAV4 Proceedings of the symposium on Testing, analysis, and verification
Automated Analysis of Concurrent Systems with the Constrained Expression Toolset
IEEE Transactions on Software Engineering
The concurrency workbench: a semantics-based tool for the verification of concurrent systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
A practical technique for bounding the time between events in concurrent real-time systems
ISSTA '93 Proceedings of the 1993 ACM SIGSOFT international symposium on Software testing and analysis
Enhancing compositional reachability analysis with context constraints
SIGSOFT '93 Proceedings of the 1st ACM SIGSOFT symposium on Foundations of software engineering
Automated Derivation of Time Bounds in Uniprocessor Concurrent Systems
IEEE Transactions on Software Engineering
Using integer programming to verify general safety and liveness properties
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
A Proposed Testing and Analysis Research Initiative
IEEE Software
Proceedings of the Fourth International Workshop on Computer Aided Verification
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Proceedings of the 5th International Conference on Computer Aided Verification
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Integer Programming in the Analysis of Concurrent Systems
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
Symbolic Bisimulation Minimisation
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Verifying General Safety and Liveness Propterties with Integer Programming
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
On-the-Fly Verification with Stubborn Sets
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Improving the precision of INCA by preventing spurious cycles
Proceedings of the 2000 ACM SIGSOFT international symposium on Software testing and analysis
Improving the Precision of INCA by Eliminating Solutions with Spurious Cycles
IEEE Transactions on Software Engineering
Using the observer design pattern for implementation of data flow analyses
Proceedings of the 2002 ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering
Towards scalable compositional analysis by refactoring design models
Proceedings of the 9th European software engineering conference held jointly with 11th ACM SIGSOFT international symposium on Foundations of software engineering
Flow analysis for verifying properties of concurrent software systems
ACM Transactions on Software Engineering and Methodology (TOSEM)
Compositional Minimization in Span(Graph): Some Examples
Electronic Notes in Theoretical Computer Science (ENTCS)
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Due to the state explosion problem, analysis of large concurrent programs will undoubtedly require compositional techniques. Existing compositional techniques are based on the idea of replacing complex subsystems with simpler processes with the same interfaces to their environments, and using the simpler processes to analyze the full system. Most algorithms for proving equivalence between two processes, however, require enumerating the states of both processes. When part of a concurrent system consists of many highly coupled processes, it may not be possible to decompose the system into components that are both small enough to enumerate and have simple interfaces with their enviornments. In such cases, analysis of the systems by standard methods will be infeasible.In this paper, we describe a technique for proving trace equivalence of deterministic and divergence-free systems without enumerating their states. (For deterministic systems, essentially all the standard notions of process equivalence collapse to trace equivalence, so this technique also establishes failures equivalence, observational equivalence, etc.) Our approach is to generate necessary conditions for the existence of a trace of one system that is not a trace of the other; if the necessary conditions cannot be satisfied the systems are equivalent. We have implemented the technique and used it to establish the equivalence of some systems with state spaces too large for enumeration to be practical.