Pipelining the adaptive decision feedback equalizer with zero latency
Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Joint AGC-equalization algorithm and VLSI architecture for wirelined transceiver designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 35.68 |
Fine-grain pipelined adaptive decision-feedback equalizer (ADFE) architectures are developed using the relaxed look-ahead technique. This technique, which is an approximation to the conventional look-ahead computation, maintains functionality of the algorithm rather than the input-output behavior. Thus, it results in substantial hardware savings as compared to either parallel processing or look-ahead techniques. Pipelining of the decision feedback loop and the adaptation loop is achieved by the use of delay relaxation and sum relaxation. Both the conventional and the predictor form of ADFE have been pipelined. Results of the convergence analysis of the proposed algorithms are also provided. The performance of the pipelined algorithms for the equalization of a magnetic recording channel is studied. It is shown that the conventional ADFE results in an SNR loss of about 0.6 dB per unit increase in the speed-up factor. The predictor form of ADFE is much more robust and results in less than 0.1 dB SNR loss per unit increase in the speed-up factor. Speed-ups of up to 8 and 45 have been demonstrated for the conventional and predictor forms of ADFE