From simulink to SCADE/lustre to TTA: a layered approach for distributed embedded applications
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Defining and translating a "safe" subset of simulink/stateflow into lustre
Proceedings of the 4th ACM international conference on Embedded software
Translating discrete-time simulink to lustre
ACM Transactions on Embedded Computing Systems (TECS)
Systems and Computers in Japan
Modularity vs. reusability: code generation from synchronous block diagrams
Proceedings of the conference on Design, automation and test in Europe
Modular Code Generation from Triggered and Timed Block Diagrams
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
Symbolic analysis for improving simulation coverage of Simulink/Stateflow models
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Modular code generation from synchronous block diagrams: modularity vs. code size
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
On identification of input/output extended automata with finite bisimilar quotients
ACC'09 Proceedings of the 2009 conference on American Control Conference
Semantic Translation of Simulink/Stateflow Models to Hybrid Automata Using Graph Transformations
Electronic Notes in Theoretical Computer Science (ENTCS)
Mining requirements from closed-loop control models
Proceedings of the 16th international conference on Hybrid systems: computation and control
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We develop a semantic translation approach for Simulink diagrams. Simulink is a graphical tool for representing and simulating dynamical systems. We propose a recursive approach for translating a class of Simulink diagrams to input/output-extended finite automata (I/O-EFA). An I/O-EFA model of a Simulink diagram can be used for further analysis such as test generation and formal verification. We show that the translation approach is sound and complete: The input-state-output behavior of an I/O-EFA model, as defined in terms of a step-trajectory, preserves the input-state-output behavior of the corresponding Simulink diagram at each sample time (assuming the same integration method for any of the continuous blocks with dynamics).