A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
System Design with SystemC
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Performance analysis of five interprocess communication mechanisms across UNIX operating systems
Journal of Systems and Software
Mambo: a full system simulator for the PowerPC architecture
ACM SIGMETRICS Performance Evaluation Review - Special issue on tools for computer architecture research
Overview of the MPSoC design challenge
Proceedings of the 43rd annual Design Automation Conference
SystemC: From the Ground Up
Linux Device Drivers, 3rd Edition
Linux Device Drivers, 3rd Edition
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Full System Simulation and Verification Framework
IAS '09 Proceedings of the 2009 Fifth International Conference on Information Assurance and Security - Volume 01
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present an interface for the hardware modeled in SystemC to access those modeled in QEMU on a QEMU and SystemC-based virtual platform. By using QEMU as the instruction-accurate instruction set simulator (IA-ISS) and its capability to run a full-fledged operating system such as Linux, the virtual platform with the proposed interface can be used to facilitate the co-design of hardware models and device drivers at the early stage of Electronic System Level (ESL) design flow. In other words, by using such a virtual platform, the hardware models and associated device drivers can be cross verified while they are being developed so that malfunctions in the hardware models or the device drivers can be easily detected. Moreover, the virtual platform with the proposed interface is capable of providing statistics of instructions executed, memory accessed, and I/O performed at the instruction-accurate level-thus not only making it easy to evaluate the performance of the hardware models but also making it possible for design space exploration.