Software reliability: measurement, prediction, application
Software reliability: measurement, prediction, application
Handbook of software reliability engineering
Handbook of software reliability engineering
FPGA-based Implementation of Signal Processing Systems
FPGA-based Implementation of Signal Processing Systems
Circuit Design and Simulation with VHDL, Second Edition
Circuit Design and Simulation with VHDL, Second Edition
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For the development of Application Specific Integrated Circuits (ASICs) for safety-related applications Hardware Description Languages (HDLs) are used. The process of such development is presented in the international standard IEC 61508, which introduces guidelines and calculations to achieve a specific Safety Integrity Level (SIL). However, it is not concerning the estimation and calculation of the reliability of used HDL codes. In this paper, a model for the quantitative evaluation of the reliability of HDL Designs is introduced. For this, conventional software reliability models (SRMs) are applied. Due to the parallel processing nature of HDL more concurrent faults can lead to a failure, therefore current SRMs need to be extended. For the execution of test cases, Field Programmable Gate Arrays (FPGAs) are useful as a prototyping platform. Through the test cases, failures are detected in the FPGA, which are configured with the hardware function of the target HDL code.