Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
An utilization driven framework for energy efficient caches
HiPC'08 Proceedings of the 15th international conference on High performance computing
An energy efficient cache design using spin torque transfer (STT) RAM
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Embedded Memories: Progress and a Look into the Future
IEEE Design & Test
Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
IEEE Transactions on Nanotechnology
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Spin-transfer torque magnetic RAM (STT MRAM) has emerged as a promising candidate for on-chip memory in future computing platforms. We present a cross-layer (device-circuit-architecture) approach to energy-efficient cache design using STT MRAM. At the device and circuit levels, we consider different genres of MTJs and bitcells, and evaluate their impact on the area, energy and performance of caches. In addition, we propose micro-architectural techniques viz. sequential cache read and partial cache line update, which exploit the non-volatility of STT MRAM to further improve energy efficiency of STT MRAM caches. A detailed comparison of STT MRAM caches with SRAM-based caches is also presented. Our results indicate that the proposed optimizations significantly enhance the efficiency of STT MRAM for designing lower level caches.