Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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For more than seventy years, all the development in digital electronics have been founded on Shannon's work based on the fact that Boolean logic operators, OR, AND and NOT, can form a computationally complete logic framework. We propose a new paradigm in logic circuit design using material implication logic operators, different from the traditional logic gates in implementation and operation. In this paper we present early evidences, with experimental silicon results, showing that this new logic framework significantly improves performance, power and speed, over an equivalent conventional-logic framework in CMOS. This new computing paradigm would enable the continuance of increasing computing functionality and performance with decreasing cost in silicon technologies.