Hierarchical correctness proofs for distributed algorithms
PODC '87 Proceedings of the sixth annual ACM Symposium on Principles of distributed computing
A formal basis for architectural connection
ACM Transactions on Software Engineering and Methodology (TOSEM)
A Classification and Comparison Framework for Software Architecture Description Languages
IEEE Transactions on Software Engineering
Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering
Behaviour Analysis of Software Architectures
WICSA1 Proceedings of the TC2 First Working IFIP Conference on Software Architecture (WICSA1)
Towards Formalizing Behavioral Substitutability in Component Frameworks
SEFM '04 Proceedings of the Software Engineering and Formal Methods, Second International Conference
Formal verification of components assembly based on SysML and interface automata
Innovations in Systems and Software Engineering
Ticc: a tool for interface compatibility and composition
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
CBSE'06 Proceedings of the 9th international conference on Component-Based Software Engineering
Specifying system architecture from SysML requirements and component interfaces
ECSA'13 Proceedings of the 7th European conference on Software Architecture
A formal verification framework for SysML activity diagrams
Expert Systems with Applications: An International Journal
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The objective of this paper is to define an approach to formalize and verify the SysML blocks in a refinement process. We propose to specify system architecture with SysML Block Definition Diagram, this diagram is then analyzed and decomposed into several sub-blocks in order to verify their compatibility. The structural architecture of an abstract block is given by the Internal Block Diagram (IBD) which defines the communication links between sub-blocks. The compatibility verification between sub-blocks is only made on linked sub-blocks. The behaviour of each sub-block is described by an interface automaton which species the invocations exchanged with its environment. The verification between blocks is translated into consistency verification between the blocks and compatibility verification between their interface automata. Incompatibilities can be inconsistent at architecture level and at communication level if there are deadlocks during the interaction between sub-blocks. Once the verification is established between the sub-blocks, the abstract block can be then substituted by the sub-blocks which compose it.