Design and performance of a multiple parallel shared memory switch

  • Authors:

  • G. Kbar

  • Affiliations:

  • Department of Communication, University of New South Wales, Sydney 2052, Australia

  • Venue:
  • Computer Communications
  • Year:
  • 1997

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Abstract

A new ATM switch architecture is presented. This switch is based on multiple parallel shared memory switches (8x8) which are connected together in a Banyan interconnection network. The parallel shared memory switch (PSMS) is capable of achieving 100% throughput under bursty traffic. This switch has the advantage of requiring a small queue size as in other types of shared memory switches. In contrast to other shared memory, there is no constraint on the switch size implementation since it does not require a speed-up which depends on the size of the switch. Speed-up is needed in the parallel shared memory switch to maintain the sequence of cells, but at a small value dependent on the size of the parallel shared memory switch element (8 in this design). The parallel shared memory switch element is based on distributed shared memory where each memory queue stores cells coming from all inputs. This limits the performance degradation that may occur in a completely shared memory where long streams from a few inputs may unfairly hog the entire space. Analysis and simulation of the switch demonstrates a high performance in terms of end-to-end delay, throughput and cell loss probability.