On the performance study of multi-plane ATM switches

  • Authors:

  • Jean-Lien C. Wu;Li-Der Chou;Hung-Fu Su

  • Affiliations:

  • Department of Electronic Engineering, National Taiwan Institute of Technology, 43, Keelung Road, Section 4, Taipei 10772, Taiwan, ROC;Department of Information Management, Central Police University, Taoyuan 33334, Taiwan, ROC;Department of Electronic Engineering, National Taiwan Institute of Technology, 43, Keelung Road, Section 4, Taipei 10772, Taiwan, ROC

  • Venue:
  • Computer Communications
  • Year:
  • 1997

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Abstract

In this paper the performance of an NxN internally nonblocking multi-plane ATM switch with common input and common output buffers is analyzed. Two traffic types are considered with different priorities. Two service policies are proposed to satisfy different performance requirements: one treats the high priority cells as loss-sensitive traffic, the other guarantees the delay time of high priority cells. The method of reflection is employed to evaluate the probability that a cell successfully leaves the input buffer. Performance measures such as throughput, delay and cell loss probability are then obtained. The effects of priority weights, traffic load and the buffer size on the performance of the proposed and the contrasted policies are studied. Besides, different traffic sources, such as Bernoulli and ON/OFF traffic sources, are also studied. The performance is significantly improved by adopting the multi-plane structure, and the two proposed service policies can guarantee the required quality of services as long as a high weight for high priority traffic class is given. Moreover, numerical results show that the delay time of the high priority traffic class for the two proposed service policies is insensitive to the buffer size, so that only cell loss probability is the key factor of concern for the design of the input buffer size.