Research: Circuit emulation approach to traffic control in a B-ISDN

  • Authors:
  • Andrea Baiocchi;Nicola Bléfari-Melazzi;Francesca Cuomo;Marco Listanti

  • Affiliations:
  • Dipartimento di Infocom, University of Roma `La Sapienza, Via Eudossiana 18, 00184 Roma, Italy;Dipartimento di Ingegneria Elettronica, University of Roma at Tor Vergata, Roma, Italy;Dipartimento di Infocom, University of Roma `La Sapienza, Via Eudossiana 18, 00184 Roma, Italy;Dipartimento di Infocom, University of Roma `La Sapienza, Via Eudossiana 18, 00184 Roma, Italy

  • Venue:
  • Computer Communications
  • Year:
  • 1997

Quantified Score

Hi-index 0.24

Visualization

Abstract

In this paper we propose a way to look at the congestion control problem in a B-ISDN that intends to gather the benefits of both circuit and packet transfer modes. We define a Circuit Emulation (CE) facility based on an admission policy at the edges of the network, and on a service discipline in the inner nodes that guarantees no information loss and no delay-jitter. On the other side, since a pure multirate-circuit emulation would be too inefficient for low bit rate bursty sources, we propose to use this facility only for a subset of the overall traffic. The CE facility is provided via the so called Worst Deterministic Pattern Allocation (WDPA) strategy, characterized by resource allocation rules as simple as those of the peak allocation. WDPA is based on the concept of preventively constraining information sources to emit their cells according to a superimposed deterministic mask. This forced regularity is exploited to control the cell transfer within the network. Practically, WDPA establishes the worst emission pattern of the source. Resource allocation is performed taking into account only the parameters of the declared deterministic mask. The same allocation rule is used in every network section. This target is achieved by means of an ad hoc defined Virtual Multiplexing Algorithm. Application of WDPA to an actual switching node based on classical output queueing is also discussed, and its compatibility with this architecture is demonstrated. A performance evaluation is carried out to highlight the benefits deriving from the proposed strategy.