A global synchronization network for a non-deterministic simulation architecture
Proceedings of the 31st conference on Winter simulation: Simulation---a bridge to the future - Volume 2
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In this paper we describe the methodology for the design and layout of fast BiCMOS ECL (emitter-couped logic) I/O buffers. Principles of ECL circuit operation are described with emphasis on the NOR/OR gate and the bandgap voltage reference. A comparison of ECL 10 K and 100 K logic families is presented as well as complete designs for an input and output buffer. The pad macros are temperature- and supply-voltage-compensated and have nominal rise and fall times of 400 ps