Cluster miss prediction for instruction caches in embedded networking applications
Proceedings of the 14th ACM Great Lakes symposium on VLSI
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This paper describes and contains the necessary VHDL files to synthesize and simulate a MIPS 32-bit RISC processor core for use in introductory computer architecture classes. This MIPS processor core is based on the design presented in chapters 5 and 6 of the widely used text, Computer Organization and Design the Hardware/Software Interface by David Patterson and John Hennessy. IEEE Standard Logic 1164 is used in the VHDL model and versions are provided for several popular CAD tools. Our experiences in using this model in our introductory computer architecture classes, CmpE 2510 and CmpE 3510, during the past two years are described along with typical laboratory assignments