Systematic software development using VDM (2nd ed.)
Systematic software development using VDM (2nd ed.)
Synthesis of ML programs in the system Coq
Journal of Symbolic Computation - Special issue on automatic programming
The B-book: assigning programs to meanings
The B-book: assigning programs to meanings
Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Subtypes for Specifications: Predicate Subtyping in PVS
IEEE Transactions on Software Engineering
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Formal Verification of Algorithms for Critical Systems
IEEE Transactions on Software Engineering
TYPES '00 Selected papers from the International Workshop on Types for Proofs and Programs
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
From ML to Ada: Strongly-typed language interoperability via source translation
Journal of Functional Programming
Interactive Theorem Proving and Program Development
Interactive Theorem Proving and Program Development
An overview of JML tools and applications
International Journal on Software Tools for Technology Transfer (STTT) - Special section on formal methods for industrial critical systems
Migration of Common Lisp Programs to the Java Platform -The Linj Approach
CSMR '07 Proceedings of the 11th European Conference on Software Maintenance and Reengineering
Formal Aspects of Computing
TYPES'02 Proceedings of the 2002 international conference on Types for proofs and programs
The Why/Krakatoa/Caduceus platform for deductive program verification
CAV'07 Proceedings of the 19th international conference on Computer aided verification
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The use of verification tools to produce formal specifications of digital systems is commonly recommended, especially when dealing with safety-critical systems. These formal specifications often consist of segments which can automatically be translated into executable code. We propose to generate both code and assertions in order to support verification at the generated code level. This is essential (and possible) when making modifications to the implemented code without revering to the verification tool, as the formal verification can be performed directly at the level of the adjusted code. As a result of a feasibility study on this approach, we present a prototype of a code generator for the Prototype Verification System (PVS) that translates a subset of PVS functional specifications into Java annotated with JML assertions. To illustrate the tool's functionality a verified communication protocol from the NASA AirStar project is taken and a reference implementation in Java is generated. Subsequently, we experiment with verification on the Java level in order to show the feasibility of proving the generated JML annotations. In this paper we report on our experiences in this feasibility study.