Goal-oriented buffer management revisited
SIGMOD '96 Proceedings of the 1996 ACM SIGMOD international conference on Management of data
System identification (2nd ed.): theory for the user
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Goal Oriented, Adaptive Transaction Routing for High Performance Transaction Processing Systems
PDIS '93 Proceedings of the 2nd International Conference on Parallel and Distributed Information Systems
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RTAS '01 Proceedings of the Seventh Real-Time Technology and Applications Symposium (RTAS '01)
Feedback Control of Computing Systems
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Design, Implementation, and Evaluation of Differentiated Caching Services
IEEE Transactions on Parallel and Distributed Systems
Managing Deadline Miss Ratio and Sensor Data Freshness in Real-Time Databases
IEEE Transactions on Knowledge and Data Engineering
Real-Time Databases and Data Services
Real-Time Systems
Specification and Management of QoS in Real-Time Databases Supporting Imprecise Computations
IEEE Transactions on Computers
Cache Replacement Algorithms with Nonuniform Miss Costs
IEEE Transactions on Computers
LGeDBMS: a small DBMS for embedded system with flash memory
VLDB '06 Proceedings of the 32nd international conference on Very large data bases
CFLRU: a replacement algorithm for flash memory
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
FlashDB: dynamic self-tuning database for NAND flash
Proceedings of the 6th international conference on Information processing in sensor networks
Design of flash-based DBMS: an in-page logging approach
Proceedings of the 2007 ACM SIGMOD international conference on Management of data
Proceedings of the 2007 ACM SIGMOD international conference on Management of data
Cost-aware WWW proxy caching algorithms
USITS'97 Proceedings of the USENIX Symposium on Internet Technologies and Systems on USENIX Symposium on Internet Technologies and Systems
Chronos: Feedback Control of a Real Database System Performance
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
QeDB: A Quality-Aware Embedded Real-Time Database
RTAS '09 Proceedings of the 2009 15th IEEE Symposium on Real-Time and Embedded Technology and Applications
A cost-aware page replacement algorithm for NAND flash based mobile embedded systems
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Design, Implementation, and Evaluation of a QoS-Aware Real-Time Embedded Database
IEEE Transactions on Computers
Power consumption breakdown on a modern laptop
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
LRU-WSR: integration of LRU and writes sequence reordering for flash memory
IEEE Transactions on Consumer Electronics
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Due to the explosive increases of data from both the cyber and physical worlds, the demand for database support in embedded systems is increasing. Databases for embedded systems, or embedded databases, are expected to provide timely in situ data services under various resource constraints, such as limited energy. However, traditional buffer cache management schemes, in which the primary goal is to minimize the number of I/O operations, is problematic since they do not consider the constraints of modern embedded devices such as limited energy and distinctive underlying storage. In particular, due to asymmetric read/write characteristics of flash memory-based storage of modern embedded devices, minimum buffer cache misses neither coincide with minimum power consumption nor minimum I/O deadline misses. In this paper we propose a novel power- and time-aware buffer cache management scheme for embedded databases. A novel multi-dimensional feedback control architecture is proposed and the characteristics of underlying storage of modern embedded devices is exploited for the simultaneous support of the desired I/O power consumption and the I/O deadline miss ratio. We have shown through an extensive simulation that our approach satisfies both power and timing requirements in I/O operations under a variety of workloads while consuming significantly smaller buffer space than baseline approaches.