VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes
Journal of Electronic Testing: Theory and Applications
Automatic generation of error control codes for computer applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Three new techniques are proposed for constructing a class of codes that extends the protection provided by previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes. The proposed codes are systematic odd-weight-column SEC-DED-SBD codes providing also the correction of any odd number of erroneous bits per byte, where a byte represents a cluster of b bits of the codeword that are fed by the same memory chip or card. These codes are useful for practical applications to enhance the reliability and the data integrity of byte-organized computer memory systems against transient, intermittent, and permanent failures. In particular they represent a good tradeoff between the overhead in terms of additional check bits and the reliability improvement, due to the capability to correct at least 50% of the multiple errors per byte