Heterogeneous multi-core platform for consumer multimedia applications
Proceedings of the Conference on Design, Automation and Test in Europe
Interframe bus encoding technique and architecture for MPEG-4 AVC/H.264 video compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The I/O power consumption in an MPEG-2 decoder is significant because of the wide connection with large capacitances to the frame buffer. To reduce the power dissipation on the memory bus, the Gray code encoding scheme is proposed to increase the correlation of the image data transferred on the bus. The bit switching probability in the re-coded data will then decrease and in turn the bus power consumption will be reduced. Combined with the proposed bus arbitration and scheduling scheme proposed in this paper, 22% reduction of power dissipation may be achieved