Development of a digital FPLL ASIC for GA HDTV receivers

Authors:
Dong-Seog Han;Myeong-Hwan Lee;Kil-Houm Park
Affiliations:
Dept. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Taegu;-;-
Venue:
IEEE Transactions on Consumer Electronics
Year:
1997

Citing 0
Cited 1

Carrier frequency synchronization based on pulse-pair method for 8-VSB DTV systems

SARNOFF'09 Proceedings of the 32nd international conference on Sarnoff symposium

Quantified Score

Hi-index	0.43

Visualization

Abstract

We propose a new digital carrier recovery loop architecture for the Grand Alliance high definition television (HDTV) system. We have developed an application specific integrated circuit (ASIC) based on the new architecture. The developed ASIC has a gate count of 60 K with a gate array technology that features 0.5 μm, 3.3 V and 2-metal-layer technology. The pull-in range of the proposed architecture is about ±250 kHz with 0 dB carrier-to-noise ratio (CNR)