An FPGA implementation of a flexible architecture for H.263 video coding

Authors:
M. J. Garrido;C. Sanz;M. Jimenez;J. M. Menesses
Affiliations:
Univ. Politecnica de Madrid, Spain;-;-;-
Venue:
IEEE Transactions on Consumer Electronics
Year:
2002

Citing 0
Cited 2

Implementing a WLAN video terminal using UML and fully automated design flow

EURASIP Journal on Embedded Systems
Scalable MPEG-4 encoder on FPGA multiprocessor SOC

EURASIP Journal on Embedded Systems

Quantified Score

Hi-index	0.43

Visualization

Abstract

The architecture and design of MVIP-2, a flexible and efficient proposal for implementing an H.263 video coder, is explained in this paper. The MVIP-2 architecture consists of a set of specialized processors for the main tasks (transforms, quantizers, motion estimation and motion compensation) and a RISC processor for the scheduling tasks. The MVIP-2 design has been written in synthesizable hardware description language (HDL) and fully tested with hardware-software co-simulation using standard video sequences. Finally, MVIP-2 has been prototyped onto a system based on an FPGA and a RISC.