A 4×4 pipelined intra frame decoder for H.264
ASID'09 Proceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication
Modeling 3D facial expressions using geometry videos
Proceedings of the international conference on Multimedia
Computation and power reduction techniques for H.264 intra prediction
Microprocessors & Microsystems
Algorithm and hardware design of a fast intra frame mode decision module for H.264/AVC encoders
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
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H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a novel technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware significantly without any PSNR and bitrate loss. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are equal, the prediction equations of H.264 intra prediction modes simplify significantly for this block. By exploiting the equality of the neighboring pixels, the proposed technique reduces the amount of computations performed by 4times4 luminance, 16times16 luminance, and 8times8 chrominance prediction modes up to 60%, 28%, and 68% respectively with a small comparison overhead. We also implemented an efficient 4times4 intra prediction hardware including the proposed technique using Verilog HDL. We quantified the impact of the proposed technique on the power consumption of this hardware on a Xilinx Virtex II FPGA using Xilinx XPower, and it reduced the power consumption of this hardware up to 18.6%.