MPEG2 video codec using image compression DSP

  • Authors:

  • T. Akiyama;H. Aono;K. Aoki;K. W. Ler;B. Wilson;T. Araki;T. Morishige;H. Takeno;A. Sato;S. Nakatani;T. Senoh

  • Affiliations:

  • Corporate Product Dev. Div., Matsushita Electr. Ind. Co. Ltd., Japan;-;-;-;-;-;-;-;-;-;-

  • Venue:
  • IEEE Transactions on Consumer Electronics
  • Year:
  • 1994

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Abstract

An MPEG2 digital video codec was developed. We estimated the amount of calculation power requested for MPEG2 and designed the architecture of the codec. In order to make the codec compact, we developed an integrated image compression digital signal processor (called VDSP2). The VDSP2 integrates four different types of processors in the architecture that allows them to operate in parallel. The device is capable of both encoding and decoding the MPEG2-based algorithm by changing programs on the same chip. We also developed new dedicated hardware for motion estimation, which consists of two-pixel precision estimation and full and half pixel precision estimation. The codec is capable of processing MPEG2 main profile at main level in real-time at broadcast resolutions