Implementing Sorting Networks with Spiking Neural P Systems
Fundamenta Informaticae
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Beginning with the recently introduced balanced sorting network, we propose a shuffle-exchange type layout consisting of a single block with the output recirculated back as input until sorting is achieved. Although this network has essentially the same performance bounds as Batcher's bitonic sort, our design has the property that no comparator in the network is critical in the sense that any faulty comparator can be bypassed without disturbing the functionality of the network (just its speed). The novelty of the design is that the robustness is derived from the underlying algorithm. The network will sort in the presence of many faulty comparators. Moreover, of the (N log N)/2 comparators, only N pairs of comparators are critical. That is, the network fails only when both comparators in a pair fail. Our results enable one to build large sorting networks on a single wafer so that a high percentage of the fabricated wafers can be used; some of the wafers will sort very quickly (the ones with no faulty components), most will sort at somewhat slower than optimal speeds, but only a few will fail to be useful as sorting networks (due to too many badly placed faults).