A fault-tolerant architecture for ATM networks

Authors:
C.-C Lo;C.-Y Chiou
Affiliations:
Institute of Information Management, National Chiao-Tung University, 1001 Ta Hsueh Road, Hsinchu 300, Taiwan;Institute of Information Management, National Chiao-Tung University, 1001 Ta Hsueh Road, Hsinchu 300, Taiwan
Venue:
Computer Communications
Year:
1999

Citing 5
Cited 0

A Survey and Comparision of Fault-Tolerant Multistage Interconnection Networks

Computer
Failure Dependent Performance Analysis of a Fault-Tolerant Multistage Interconnection Network

IEEE Transactions on Computers
A fault-tolerant scheme for multistage interconnection networks

ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
On a Class of Multistage Interconnection Networks

IEEE Transactions on Computers
A Class of Redundant Path Multistage Interconnection Networks

IEEE Transactions on Computers

Quantified Score

Hi-index	0.24

Visualization

Abstract

The asynchronous transfer mode (ATM) is the transfer mode recommended for the broad integrated service digital network (B-ISDN) by ITU-T. In this paper, we propose a self-routing fault-tolerant switching architecture for ATM networks. The proposed architecture uses subswitches and extra links to provide alternative paths; hence, can tolerate multiple faults. Analytical results show that the total number of redundant paths increases exponentially as the size of the network increases. A simulation model is developed. Simulation results indicate that the proposed architecture is much more fault-tolerant and cost-effective than those architectures found in the literature. Simulation results also illustrate that the proposed architecture still maintains a high throughput with an acceptable cell delay time, even when the number of faulty elements increases.