Dimensioning bandwidth for elastic traffic in high-speed data networks
IEEE/ACM Transactions on Networking (TON)
SRR: An O(1) time complexity packet scheduler for flows in multi-service packet networks
Proceedings of the 2001 conference on Applications, technologies, architectures, and protocols for computer communications
A game-theoretic approach towards congestion control in communication networks
ACM SIGCOMM Computer Communication Review
Load Estimation and Control in Best-Effort Network Domains
Journal of Network and Systems Management
QoS-IP '01 Proceedings of the International Workshop on Quality of Service in Multiservice IP Networks
SRR: an O(1) time-complexity packet scheduler for flows in multiservice packet networks
IEEE/ACM Transactions on Networking (TON)
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Providing quality-of-service guarantees in both cell- and packet-based networks requires the use of a scheduling algorithm in the switches and network interfaces. These algorithms need to be implemented in hardware in a high-speed switch. The authors present a number of approaches to implement scheduling algorithms in hardware. They begin by presenting a general methodology for the design of timestamp-based fair queuing algorithms that provide the same bounds on end-to-end delay and fairness as those of weighted fair queuing, yet have efficient hardware implementations. Based on this general methodology, the authors describe two specific algorithms, frame-based fair queuing and starting potential-based fair queuing, and discuss illustrative implementations in hardware. These algorithms may be used in both cell switches and packet switches with variable-size packets. A methodology for combining a traffic shaper with this class of fair queuing schedulers is also presented for use in network interface devices, such as an ATM segmentation and reassembly device