Image understanding architecture and applications
Advances in Machine Vision
Connection autonomy in SIMD computers: a VLSI implementation
Journal of Parallel and Distributed Computing
Meshes with reconfigurable buses
Proceedings of the fifth MIT conference on Advanced research in VLSI
Parallel Architectures and Algorithms for Image Component Labeling
IEEE Transactions on Pattern Analysis and Machine Intelligence
Efficient parallel algorithms for some graph problems
Communications of the ACM
Concrete Math
IEEE Transactions on Parallel and Distributed Systems
Constant-Time Parallel Algorithms for Image Labeling on a Reconfigurable Network of Processors
IEEE Transactions on Parallel and Distributed Systems
Scaling Simulation of the Fusing-Restricted Reconfigurable Mesh
IEEE Transactions on Parallel and Distributed Systems
Using bus linearization to scale the reconfigurable mesh
Journal of Parallel and Distributed Computing
| Hi-index | 0.00 |
This short note presents constant-time algorithms for labeling the connected components of an image on a network of processors with a wide reconfigurable bus. The algorithms are based on a processor indexing scheme which employs constant-weight codes. The use of such codes enables identifying a single representative processor for each component in a constant number of steps. The proposed algorithms can label an N×N image in O(1) time using N2 processors, which is optimal. Furthermore, the proposed techniques lead to an O(logN/loglogN)-time image labeling algorithm on a network of N2 processors with a reconfigurable bus of width log N bits. It is shown that these techniques on be applied to labeling an undirected N-vertex graph represented by an adjacency matrix