A host-network interface architecture for ATM
SIGCOMM '91 Proceedings of the conference on Communications architecture & protocols
A high-performance host interface for ATM networks
SIGCOMM '91 Proceedings of the conference on Communications architecture & protocols
A parallel embedded-processor architecture for ATM reassembly
IEEE/ACM Transactions on Networking (TON)
Design and Implementation of a High-Speed ATM Host Interface Controller
ICOIN '98 Proceedings of the 13th International Conference on Information Networking
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The use of a general purpose processing core in the design of high-speed network interfaces can be very useful in providing some important features to these interfaces, such as simplicity, shorter developing cycle time, low development cost, and flexibility. However, it is not clear whether such a core can efficiently provide the processing power required by these high-speed interfaces without significantly increasing the clock rate of the processing core. Such an increase will make the cost of the core very high and not practical to be used with Asynchronous Transfer Mode (ATM) interfaces. In this paper, we have demonstrated that a general purpose processing core, such as an 80MHz Reduced Instruction Set Computer (RISC), can be used in ATM network interfaces for a wide range of transmission line speeds, up to 1.2Gb/s. Also, we have discussed some of the design issues related to the RISC core based network interfaces.