Design and analysis of per-flow queueing switches and VC-merge switches based on per-VC queueing architecture

Authors:
P. Zhou;O. Yang
Affiliations:
School of Information Technology and Engineering, University of Ottawa, Ottawa, Ontario, Canada K1N 6N5;School of Information Technology and Engineering, University of Ottawa, Ottawa, Ontario, Canada K1N 6N5
Venue:
Computer Communications
Year:
2000

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Abstract

In this paper, we apply to the router design, the Multi Protocol Label Switching (MPLS) paradigm, which integrates layer-3 routing with layer-2 switching. We propose per-flow queueing in access routers and VC merging in core routers. The contributions of this paper are to demonstrate that ATM's per-VC queueing architecture is instrumental to both per-flow queueing and VC merging, and to study the impact of VC merging on the buffer requirement. Results indicate that buffer requirement of VC merging can be excessive when compared to non-VC merging. This is in contrast to previous findings [14] [I. Widjaja, A. Elwalid, Performance issues in VC-merge capable switches for IP over ATM networks, Proceedings of the IEEE INFOCOM-98, San Francisco, CA, 1998, pp. 372-380], and it has important implications for designing core routers when MPLS is used. We propose two schemes to significantly reduce the buffer requirement in MPLS core routers.