Performance analysis of BusNet protocol for backplane bus-based interprocessor communication

Authors:
Minyoung Sung;Naehyuck Chang;Jinsung Cho;Heonshik Shin
Affiliations:
School of Computer Science and Engineering, Seoul National University, Seoul 151-742, South Korea;School of Computer Science and Engineering, Seoul National University, Seoul 151-742, South Korea;School of Computer Science and Engineering, Seoul National University, Seoul 151-742, South Korea;School of Computer Science and Engineering, Seoul National University, Seoul 151-742, South Korea
Venue:
Computer Communications
Year:
2001

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Abstract

Nowadays, backplane bus-based multiprocessor systems often utilize the standard network protocol such as TCP/IP for communication between processors on the backplane bus. In such systems, it is common for the backplane bus to emulate the standard MAC protocols such as CSMA/CD. This paper aims to analyze the delay performance of the MAC emulation-based backplane network by constructing queueing models based on detailed bus operations. For this purpose, we choose BusNet as a target protocol. BusNet is an ANSI standard network protocol and its specification contains basic operations commonly used in most backplane buses. We investigate the throughput-delay characteristics in terms of packet size, block transfer scale, and arbitration scheme. We also compare the packet delay in BusNet with the IEEE 802.3 CSMA/CD network which BusNet is expected to be compatible with. The simulation result shows how an optimal block transfer scale can be determined in respect of the performance trade-off between BusNet and other real-time traffics.