A timing analysis algorithm for circuits with level-sensitive latches

Authors:
Jin-Fuw Lee;D. T. Tang;C. K. Wong
Affiliations:
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

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Abstract

For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the modified shortest and longest path method. The computational complexity of our algorithm is generally better than that of known algorithms in the literature. The implementation (CYCLOPSS) has been applied to an industrial chip to verify the clock schedules