Parallelizing post-placement timing optimization
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Efficient and Deterministic Parallel Placement for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. Our algorithm is a derivative of simulated annealing. The implementation of our algorithm is targeted toward networks of Unix workstations. This is the very first reported parallel algorithm for standard cell placement which yields as good or better placement results than its serial version. In addition, it is the first parallel placement algorithm reported which offers nearly linear speed-up for small numbers of processors, in terms of the number of processors (workstations) used, over the serial version. Despite using the rather slow local area network as the only means of interprocessor communication, the processor utilization is quite high, up to 98% for two processors and 90% for six processors. The new parallel algorithm has yielded the best overall results ever reported for the set of MCNC standard cell benchmark circuits