A Hierachical Method for Wiring and Congestion Prediction
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Block placement to ensure channel routability
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Interconnect estimation for mesh-based reconfigurable computing
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
A novel fault diagnosis mechanism for wireless sensor networks
Mathematical and Computer Modelling: An International Journal
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This paper presents a new stochastic model for two-dimensional layouts of large size. Two problems are addressed. (1) Under the condition that the number of wires emanating from a block is Poisson distributed, determine the distribution of channel width, thus estimating the average channel width. (2) Given T tracks for each channel, determine the success probability of routing an M×M cell array chip. For both problems, closed formulas are obtained. The experiment demonstrates the effectiveness of our approach. The results can be applied to gate array, field-programmable gate array design, etc