Verifying the correctness of FPGA logic synthesis algorithms
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
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This paper describes a new procedure for generating very large realistic benchmark circuits which are especially suited for the performance evaluation of field programmable gate array partitioning algorithms. These benchmark circuits can be generated quickly. The generation of a netlist of 100 K configurable logic blocks (500 K equivalent gates), for instance, takes only 2 min on a standard UNIX workstation. The analysis of a large number of netlists from real designs lead us to identify the following five different kinds of subblocks: regular combinational logic, irregular combinational logic, combinational and sequential logic, memory blocks, and interconnections. Therefore, our generator integrates a subgenerator for each of these types of netlist. The comparison of the partitioning results of industrial netlists with those obtained from generated netlists of the same size shows that the generated netlists behave similarly to the originals in terms of average filling rate and average pin utilization