Proceedings of the 9th annual conference on Genetic and evolutionary computation
System-level simulation for continuous-time delta-sigma modulator in MATLAB SIMULINK
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
Reconfigurable ΔΣ modulator topology design through hierarchical mapping and constraint extraction
Integration, the VLSI Journal
DISCO: a graphical methodology for the design of Sigma-Delta modulators
Analog Integrated Circuits and Signal Processing
Efficient simulation of weak nonlinearities in continuous-time oversampling converters
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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Circuit-level simulation of ΔΣ modulators is a time-consuming task, taking one or more days for meaningful results. While there are a great variety of techniques and tools that speed up the simulations for discrete-time ΔΣ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time counterpart. Nevertheless, in today's low-power, high-accuracy and/or very high-speed demands for A-to-D converters, designers are often forced to resort to the use of continuous-time ΔΣ topologies. In this paper, we present a method for the high-level simulation of continuous-time ΔΣ modulators as needed in top-down design and high-level modulator optimization. The method is based on analytical integration using behavioral models and exhibits the best tradeoff between accuracy, speed, and extensibility in comparison with other possible techniques that are reviewed briefly in this work. This methodology has been implemented in a user-friendly tool. Nonidealities such as finite gain, finite GBW, output impedance, and also nonlinearities, such as clipping, harmonic distortion, and the important effect of jitter are modeled. Finally, the tool was used to carry out some design-relevant experiments, illustrating the straightforward way of obtaining and exploring design tradeoffs at the modulator architectural level.