Single-Layer Routing for VLSI: Analysis and Algorithms

Authors:
M. Marek-Sadowska;Tom Tsan-Kuo Tarng
Affiliations:
-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

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Planar subset of multi-terminal nets

Integration, the VLSI Journal

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Abstract

In this paper we present a discussion of planarity testing and detailed single-layer routing. A program which implements the proposed algorithms for routing nets inside an arbitrarily shaped region has been written and tested. The results from this program are shown as examples.