Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a built-in test method targeting interconnect defects using IDDT testing, delay testing, and boundary scan. It was learned that IDDT testing is an effective way to detect open and short defects. Boundary scan can provide accessibility to internal buses inside a chip. A statistical analysis method eases the uncertain factors due to process variations and power fluctuation. This paper also includes the experimental data using the proposed techniques to detect shorts, opens, or the other non-stuck-at fault type defects.