Design closure driven delay relaxation based on convex cost network flow
Proceedings of the conference on Design, automation and test in Europe
Non-linear statistical static timing analysis for non-Gaussian variation sources
Proceedings of the 44th annual Design Automation Conference
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The problem of retiming over a netlist of macroblocks to achieve minimal clock period, where block internal structures may not be changed and flip-flops may not be inserted on some wire segments, is called the optimal wire retiming problem. This paper presents a new algorithm that solves the optimal wire retiming problem with polynomial-time worst case complexity. Since the new algorithm avoids binary search and is essentially incremental, it has the potential of being combined with other optimization techniques. Experimental results show that the new algorithm is very efficient in practice