Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors propose a low-power testing methodology for the scan-based built-in self-test. This approach combines a low-power test pattern generator (TPG) with scan-chain reordering to achieve low-power testing without losing fault coverage. Three main issues are addressed. First, a smoother is included in the TPG to reduce the average power consumption. However, the fault coverage may be adversely affected by the smoother; hence, a cluster-based scan-chain reordering is employed to remedy this problem. If a very-large power reduction is necessary, the fault-coverage drop can become significant. This can be addressed by reseeding. The second topic of this paper is to give a detailed analysis on the optimal cluster size to minimize the scan-chain length. Finally, a fast and efficient algorithm is developed for scan-chain reorder in order to improve the fault coverage. The reordering algorithm is very efficient in terms of computation time, and the routing length of the reordered scan chain is comparable to or smaller than the result given by commercial tools. Experimental results show that the proposed method provides a significant and consistent reduction in the average test power, and the fault coverage is similar to previous methods with the same test lengths