A new time-stepping method for circuit simulation
Proceedings of the 50th Annual Design Automation Conference
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In this paper, the Newton-Krylov method is explored for robust and efficient time-domain simulation of integrated circuits with large amount of parasitic elements. Different from LU-factorization-based direct methods used in SPICE-like circuit simulators, the Newton-Krylov method uses a preconditioned Krylov-subspace iterative method for solving linearized-circuit equations. A key contribution of this paper is to introduce an effective quasi-Newton preconditioning scheme for Krylov-subspace methods to reduce the number and cost of LU factorization during an entire time-domain circuit simulation. The proposed quasi-Newton preconditioning scheme consists of four key techniques: 1) a systematic method for adaptively controlling time step sizes; 2) automatically generated piecewise weakly nonlinear (PWNL) definition of nonlinear devices to construct quasi-Newton preconditioners; 3) low-rank update techniques for incrementally updating preconditioners; and 4) incomplete-LU preconditioning for efficiency. Experimental results on a collection of digital, analog, and RF circuits have shown that the quasi-Newton preconditioned Krylov-subspace method is as robust and accurate as the direct method used in SPICE. The proposed Newton-Krylov method is attractive for simulating circuits with massive parasitic RLC elements for postlayout verification. For a nonlinear circuit with power/ground networks with tens-of-thousand elements, the CPU time speedup over SPICE3 is over 20X, and it is expected to increase further with the circuit size