Uncertainty-aware dynamic power management in partially observable domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to the gate and wire variability. Therefore, statistical timing analysis (denoted by sigmaTA) is becoming unavoidable. In this paper, two new approaches for doing variational gate TA for Gaussian and non-Gaussian sources of variation in parameterized sigmaTA are presented. To start, a variational RC-pi load is approximated by using a canonical first-order model. Next, an accurate variational gate TA (VGTA) technique, which accounts for variational RC-pi loads, variational input transitions, and a variation-aware gate library, is introduced. The proposed method relies on static effective-capacitance-calculation method and its variational form. Experimental results demonstrate that VGTA exhibits an average error of 4% for gate delay and output transition time with respect to the Monte Carlo simulation with 104 samples. Next, a more efficient VGTA [called Fast VGTA (F-VGTA)] based on a single-iteration variational effective capacitance calculation is presented. Experimental results show that F-VGTA achieves an average error of 7% for gate delay and output transition time with respect to the Monte Carlo simulation with 104 samples but with runtimes that are about two times faster than VGTA.