Fast statistical analysis of process variation effects using accurate PLL behavioral models
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Interconnect performance corners considering crosstalk noise
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate characterization of the variability in power consumption in modern mobile processors
HotPower'12 Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems
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An analytical gate delay model is developed by integrating short-channel effects and the Alpha-power law-based timing model. As verified with an industrial 90-nm technology, this analytical approach accurately predicts both nominal delay and delay variability over a wide range of power supply conditions including subthreshold and strong- inversion regions. Excellent model scalability enables efficient mapping between process variations and delay variability at the gate level. Based on this model, the impact of various physical effects on delay variability has been identified. While the variation of effective channel length is the leading source for delay variability at the current 90-nm node, delay variability is actually more sensitive to the variation of threshold voltage, especially in the subthreshold region. Furthermore, the limitation of low-power design techniques is investigated in the presence of process variations, particularly dual Vth and L biasing. These techniques become less effective at low VDD due to excessive delay variability.