Register File Power Reduction Using Bypass Sensitive Compiler

Authors:
Sanghyun Park;A. Shrivastava;N. Dutt;A. Nicolau;Yunheung Paek;E. Earlie
Affiliations:
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul;-;-;-;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2008

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Abstract

This paper explores, develops, and investigates several bypass-sensitive compilation techniques to reduce the register file power by reducing the access frequency to the register file. We study the effectiveness of our techniques on the Intel XScale processor, which is based on the previously proposed ldquoon-demand register fetch readrdquo architectural feature. Furthermore, we show that our bypass-sensitive compilation technique is effective on various partial bypass configurations.