The relationship between design and verification

• Authors: M. Hamilton;S. Zeldin
• Venue: Journal of Systems and Software
• Year: 1984

The assumption is made here that a design process, in order to be effective, must include techniques that facilitate the effectiveness of the verification of the target design resulting from that process. The assumption is also made that these techniques can and should be universal in nature. That is, any system designer should be able to use these techniques to benefit his or her own design process and to check for the proper use of these techniques, both statically and automatically, with the aid of a common set of tools. Once a set of universal techniques has been verified, there is no longer a need to verify such techniques each time a new system is designed. It follows, then, that there is no longer a need to verify or prevent those categories of problems that are known to exist no longer, given the correct use of those system design techniques that eliminates that class of problems. Verification of a system design includes the identification of redundancies, logical incompleteness, and inconsistencies of a system definition, description, implementation, and execution. If a system design process inherently produces a design that no longer requires certain types of ''after the fact'' verification, many aspects previously associated with the verification process can be eliminated. We discuss our recent experiences in defining systems where we have attempted to show the relationship between design and verification. An example specification is used to demonstrate the properties of a system definition whose design supports elimination of unnecessary verification, maximum use of static verification, and minimum use of dynamic verification.