Gigaflops in linear programming

  • Authors:
  • Irvin J. Lustig;Edward Rothberg

  • Affiliations:
  • CPLEX Optimization, Ine., 930 Tahoe Boulevard, Buildiny 802-279, Incline Village, NV 89451, USA;Silicon Graphics, Inc., 2011 N. Shoreline Blvd, Mountain View, CA 94043, USA

  • Venue:
  • Operations Research Letters
  • Year:
  • 1996

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Abstract

This paper describes the parallelization of an ''industrial strength'' linear programming package. Our parallel version of CPLEX Barrier, running on a Silicon Graphics Power Challenge shared-memory multiprocessor, provides dramatic performance improvements over sequential methods on a wide range of practical, realistic linear programming problems. The resulting software/hardware combination can provide sustained performance of as much as 2.4 Gflops.