Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
Information Theory, Inference & Learning Algorithms
Information Theory, Inference & Learning Algorithms
Trellis and Turbo Coding
Switching Activity in Stochastic Decoders
ISMVL '10 Proceedings of the 2010 40th IEEE International Symposium on Multiple-Valued Logic
The capacity of low-density parity-check codes under message-passing decoding
IEEE Transactions on Information Theory
Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation
IEEE Transactions on Information Theory
A recursive approach to low complexity codes
IEEE Transactions on Information Theory
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LDPC codes can be designed to perform extremely close to the Shannon limit. Achieving such performance with high energy efficiency is now a main goal in the research community. This work combines knowledge of LDPC decoder message statistics, provided by density evolution, with knowledge of the physical implementation of decoders to predict switching activity in the decoder interconnect. In this work we provide results for the switching activity on the interconnect for fully parallel decoders. However, our model can be applied to partially parallel and serial implementations, and is not limited to interconnect. It is shown that switching activity can vary by as much as 300%, depending on several hardware design choices. Results of this work validate the usefulness of the presented model for providing designers with an understanding of how their decoder implementation choices affect power consumption for any size of LDPC code. This knowledge can be used for making design choices that minimize decoder power consumption very early in the hardware design process.