The architecture and implementation of a high-speed host interface

• Authors: B. S. Davie
• Venue: IEEE Journal on Selected Areas in Communications
• Year: 2006

In the design of a high-speed network, the host network interface is a critical component in achieving high end-to-end throughput. Some of the architectural issues involved in host interfacing are discussed. These include the appropriate partitioning of functionality between host and interface and the choice of mechanism for data movement into, out of, and within the host. The general issues are considered in a specific example: the realization of a highly flexible host interface for a 622-Mb/s asynchronous transfer mode network. The architecture of such an interface is described, and the experimental results obtained from its prototype implementation are presented. The prototype will allow experimentation with a variety of scheduling and segmentation/reassembly algorithms, and with new transport protocols, while also delivering high bandwidths to the host